Split gate device with doped region and method therefor

ABSTRACT

A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

BACKGROUND

Field

This disclosure relates generally to semiconductor processing, and morespecifically, to a split gate device with a doped region and methodtherefor.

Related Art

Nonvolatile memories are an important element in the design ofelectronic devices. An NVM is typically constructed with a plurality ofNVM cells, each of which includes a separate charge storage element forstoring electrical charge. One type of NVM uses split gate devices, inwhich each split gate device exhibits two distinguishable channelregions, respectively controllable by a select gate and a control gate.In one example, the control gate overlaps the select gate with a chargestorage layer between the control gate and the select gate and betweenthe control gate and the substrate. However, as the devices decrease insize, the issue of charge trap-up has become increasingly problematic.Trap-up results from trapped charges in the dielectric of the chargestorage layer and is most significant at the source edge, wherein thecontrol gate is closest to the substrate. During cycling, these trappedcharges are difficult to remove and negatively impact the thresholdvoltage. Therefore, a need exists for an improved split-gate devicewhich reduces the effects of the trapped charges.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notlimited by the accompanying figures, in which like references indicatesimilar elements. Elements in the figures are illustrated for simplicityand clarity and have not necessarily been drawn to scale.

FIGS. 1-6 illustrate a semiconductor device at various processing stagesin accordance with one embodiment of the present invention.

FIGS. 7-8 illustrate a second semiconductor device at various processingstages in accordance with one embodiment of the present invention.

FIGS. 9-11 illustrate a third semiconductor device at various processingstages in accordance with one embodiment of the present invention.

FIGS. 12-13 illustrate a fourth semiconductor device at variousprocessing stages in accordance with one embodiment of the presentinvention.

FIGS. 14-15 illustrate a fifth semiconductor device at variousprocessing stages in accordance with one embodiment of the presentinvention.

DETAILED DESCRIPTION

In a split gate structure, a selective implant through part of thecontrol gate layer places dopants at the channel surface region near thesource edge. This implanted regions shields the trapped charges so as toreduce their influence on the bit cell's electrical characteristics.This implant region may be formed in a variety of ways at differentprocessing stages.

FIG. 1 illustrates a cross-sectional view of a semiconductor structure10 at a processing stage. Structure 10 includes a semiconductorsubstrate 12 having isolation regions 14 and 16. Isolations regions 14and 16 may be formed as known in the art with any dielectric material,such as, for example, an oxide. Substrate 12 also includes well 18formed between isolation regions 14 and 16, and a well 20 formed betweenisolation region 16 and an adjacent isolation region (not shown in thecross-section of FIG. 1). In one embodiment, well 18 is a p-type welland well 20 is an n-type well. Structure 10 includes a select gate 24formed over substrate 12 and a select gate 30 formed over substrate 12,laterally spaced apart from select gate 24. A gate dielectric 22 islocated between select gate 24 and substrate 12 and a gate dielectric 28is located between select gate 30 and substrate 12. Select gates 24 and30 are formed over well 18. Structure 10 also includes a gate portion 36formed over well 20 of substrate 12. A gate dielectric 34 is locatedbetween gate portion 36 and substrate 12. Each of select gate 24, selectgate 30 and gate portion 36 have an anti-reflective coating (ARC) formedon top, such as ARC 26 formed on select gate 24, ARC 32 formed on selectgate 30, and ARC 38 formed on gate portion 36. In one embodiment, a gatedielectric layer is formed over substrate 12, a gate layer is blanketdeposited over the gate dielectric layer, and an ARC layer is blanketdeposited over the gate layer. This stack of layers is then patterned toform select gate 24, select gate 30, and gate portion 36, along with thecorresponding gate dielectrics and ARCs. In one embodiment, the gatedielectric layer includes oxide, the blanket deposited gate layerincludes polysilicon, and the ARC layer includes nitride, oxide, or acombination thereof. Semiconductor substrate 12 can be any semiconductormaterial or combinations of materials, such as gallium arsenide, silicongermanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon,the like, and combinations of the above.

Still referring to FIG. 1, a charge storage layer 40 is formed oversubstrate 12, including over select gate 24, select gate 30, and gateportion 36. Charge storage layer 40 may include one or more layers, suchas a nitride layer, an oxide layer, or a combination thereof.Alternatively, charge storage layer 40 may include discrete chargestorage elements, such as nanocrystals. The discrete charge storageelements may be, for example, polysilicon, and may be surrounded by aninsulator material such as oxide. In yet another embodiment, floatinggate devices may be formed in which charge storage layer 40 would bereplaced with a first dielectric layer, a floating gate, and a seconddielectric layer. A control gate layer 42 is then formed over chargestorage layer 40. Control gate layer 42 is conformal over charge storagelayer 40 and may be blanket deposited. Control gate layer 42 may includepolysilicon and have a thickness in a range of 60 to 150 nanometers, oralternatively, 80 to 120 nanometers. In one embodiment, each of selectgates 24 and 30 are doped with an n-type dopant and control gate layer42 is undoped. Note that control gate layer 42 has a top surface furtherfrom a top surface of substrate 12 in a first region 13 over andlaterally adjacent select gate 24 and a second region 17 over andlaterally adjacent select gate 30 than in a third region 15 betweenselect gates 24 and 30.

FIG. 2 illustrates a cross-sectional view of structure 10 at asubsequent processing stage. An implant 44 is performed to result indoped regions 47, 46, and 48. In one embodiment, an n-type implant isperformed using a dopant such as, for example, phosphorous, arsenic, orantimony. Implant 44 is performed with an energy (or strength) such thata fraction of the dopants will penetrate through control gate layer 42in region 15 into substrate 12 but not penetrate though control gatelayer 42 in regions 13 and 17. Therefore, implant 44 only results indoped regions under those sections of control gate layer 42 in which thetop surface is closer to the top surface of substrate 12, where thedopant has to penetrate less gate material (control gate material orselect gate material). As seen in FIG. 2, the “shoulders” of controlgate layer 42 on either side of the select gates in regions 13 and 17are much thicker than control gate layer 42 in region 15. ARC layers 26,32, and 38 also help stop the dopants from implant 44 from enteringselect gates 24 and 30 and gate portion 36. In one embodiment, dopedregions 47, 46, and 48 have a resulting dopant concentration of 10¹⁸ to10²⁰/cm³. In one embodiment, this concentration is about 2 orders ofmagnitude less than the source/drain regions of each device (to beformed at a later processing stage). In one embodiment, doped regions47, 46, and 48 have a depth of about 10 to 100 nanometers into substrate12. Alternatively, if a p-type implant is performed (such as if thedevices formed are of an opposite conductive type), boron may be used asthe dopant.

FIG. 3 illustrates a cross-sectional view of structure 10 at asubsequent processing stage. An ARC layer 50 is formed over control gatelayer 42. ARC layer 50 includes an insulating layer, such as nitride oroxynitride.

FIG. 4 illustrates a cross-sectional view of structure 10 at asubsequent processing stage. ARC layer 50, control gate layer 42 andcharge storage layer 40 are patterned to result in a split gate device64 having a charge storage layer 52 and a control gate 54, and a splitgate device 66 having a charge storage layer 58 and a control gate 60.Split gate device 64 includes select gate 24 with charge storage layer52 (formed from charge storage layer 40) and control gate 54 (formedfrom control gate layer 42) overlapping and along a first sidewall ofselect gate 24. Therefore, charge storage layer 52 is located betweencontrol gate 54 and a top surface of select gate 24, between controlgate 54 and the first sidewall of select gate 24, and between controlgate 54 and substrate 12. Split gate device 64 also includes ARC 56(formed from ARC layer 50). Split gate device 66 includes select gate 30with charge storage layer 58 (formed from charge storage layer 40) andcontrol gate 60 (formed from control gate layer 42) overlapping andalong a first sidewall of select gate 30. Therefore, charge storagelayer 58 is located between control gate 60 and a top surface of selectgate 30, between control gate 60 and the first sidewall of select gate30, and between control gate 60 and substrate 12. Split gate device 66also includes ARC 62 (formed from ARC layer 50).

Therefore, the patterning removes a portion of charge storage layer 40,control gate layer 42, and ARC layer 50 from over a first portion 67 ofdoped region 46 between select gates 24 and 30. Control gate 54 is oversubstrate 12 adjacent select gate 24 over a second portion 69 of dopedregion 46, and control gate 60 is over substrate 12 adjacent select gate30 over a third portion 71 of doped region 46. Doped region 46 thereforeextends under both control gate 54 (such as region 69) and control gate60 (such as region 71). In one embodiment, doped region 46 extends undercontrol gate 54 to a point at least a fourth of the way across controlgate 54 and under control gate 60 to a point at least a fourth of theway across control gate 60. The patterning also removes charge storagelayer 40, control gate layer 42, and ARC layer 50 from over gate portion36.

FIG. 5 illustrates a cross-sectional view of structure 10 at asubsequent processing stage. ARCs 56, 62, and 38 are removed, as well asexposed portions of ARCs 26 and 32. Gate portion 36 and gate dielectric34 are also patterned so as to form a gate and gate dielectric ofanother device 68, such as, for example, a logic device.

FIG. 6 illustrates a cross-sectional view of structure 10 at asubsequent processing stage. Sidewall spacer 72 is formed around splitgate device 64, sidewall spacer 74 is formed around split gate device66, and sidewall spacer 76 is formed around device 68. Sidewall spacer72 is formed along a second sidewall of select gate 24 opposite thefirst sidewall, along a first sidewall of control gate 54 on top ofselect gate 24, along a second sidewall of control gate 54 on top ofsubstrate 12, and along an outer surface portion (i.e. a third sidewall)of control gate 54 between the first and second sidewalls of controlgate 54. Sidewall spacer 74 is formed along a second sidewall of selectgate 30 opposite the first sidewall, along a first sidewall of controlgate 60 on top of select gate 30, along a second sidewall of controlgate 60 on top of substrate 12, and along an outer surface portion (i.e.a third sidewall) of control gate 60 between the first and secondsidewalls of control gate 60. Sidewall spacer 76 is formed along firstand second sidewalls of gate 36. Sidewalls 72, 74, and 76 may be formed,for example, by forming an insulating layer and performing ananisotropic etch.

Source/drain (S/D) regions 78, 80, and 82 are formed in well 18, and S/Dregions 84 and 86 are formed in well 20. S/D region 80 is formed betweenthe second sidewall of control gate 54 and the second sidewall ofcontrol gate 60, between spacers 72 and 74. S/D region 80 is formedthrough portion 67 of doped region 46. S/D region 78 is formed in well18 adjacent the second sidewall of select gate 24, and a portion of S/Dregion 78 extends under the second sidewall of select gate 24. S/Dregion 82 is formed in well 18 adjacent the second sidewall of selectgate 30, and a portion of S/D region 82 extends under the secondsidewall of select gate 30. S/D region 84 is formed in well 20 adjacenta first sidewall of gate 36 and extends under the first sidewall of gate36, and S/D region 86 is formed in well 20 adjacent a second sidewall ofgate 36 and extends under the second sidewall of gate 36. Note that eachof S/D regions 78, 82, 84, and 86 can be formed using two differentimplants. A first shallow implant may be used to form extensions priorto spacer formation, and a second deep implant may be used to form thedeep source/drains after spacer formation. S/D region 80 may be formedwith just the deep implant, without extensions, and is shared by splitgate device 64 and 66. Split gate devices 64 and 66 may form a part of anon-volatile memory structure that includes any number of bit cells withsplit gate devices.

S/D regions 78, 80, and 82 extend deeper into substrate 12 as comparedto doped region 46. In one embodiment, the depths of S/D region 80 anddoped region 46 has a ratio in a range of about 2 to 15. Also, the S/Dregions are implanted with the same conductivity type as region 46, butwith a concentration of about 2 magnitudes greater that the S/D regions.Doped region 46 extends under the corner formed by control gate 54 atthe second sidewall of control gate 54, adjacent S/D region 80, andunder the corner formed by control gate 60 at the second sidewall ofcontrol gate 60, adjacent S/D region 80. S/D region 80 corresponds tothe source of split gate devices 64 and 66, and trap up is usually worseat the source side. Therefore, by doped region 46 extending under thesecorners, the trapped charges can be shielded, thus reducing theireffects on the devices. Note that doped region 46 is also spaced apartfrom each of select gate 24 and 30 so as not to adversely impactoperation.

FIG. 7 illustrates a cross-sectional view of structure 10 according toan alternate embodiment in which like numerals indicate like elements.Referring back to the processing stage of FIG. 1, in which control gatelayer 42 has been formed conformally over charge storage layer 40,rather than performing implant 44 (as in FIG. 2), ARC layer 50 is firstformed over control gate layer 42. After forming ARC layer 50, implant90 is performed, which is similar to implant 44. Implant 90 is performedwith an energy (or strength) such that a fraction of the dopants willpenetrate through ARC layer 50 and control gate layer 42 into substrate12 to result in doped region 92, 94, and 96 but not penetrate ARC layers26 and 32 and control gate layer 42 in regions 13 and 17. Therefore,doped region 94 in region 15 is similar to doped region 46 (and can havesimilar dopant types and concentrations) but is laterally shiftedinwards at both ends. That is, doped region 94 is spaced apart fromselect gates 24 and 30 farther than doped region 46 is spaced apart fromselect gates 24 and 30. This is due to the added thickness of ARC layer50 that is present before the implant, making regions 13 and 17 widerand region 15 narrower.

FIG. 8 illustrates a cross-sectional view of structure 10 as processedin accordance to the alternate embodiment described in FIG. 7. That is,the subsequent processing may be the same as described above inreference to FIGS. 4-6 to form split gate devices 64 and 66. Therefore,depending on the desired width of doped regions 46 and 94, the implant44 or 90 may be performed before or after formation of ARC layer 50 overcontrol gate layer 42. As with doped region 46, doped region 94 extendsunder the corner formed by control gate 54 at the second sidewall ofcontrol gate 54, adjacent S/D region 80, and under the corner formed bycontrol gate 60 at the second sidewall of control gate 60, adjacent S/Dregion 80. Therefore, doped region 94 similarly shields the trappedcharges, thus reducing their effects on the devices.

FIG. 9 illustrates a cross-sectional view of a semiconductor structure100 according to an alternate embodiment in which like numerals indicatelike elements. Referring back to the processing stage of FIG. 1, ratherthan performing implant 44 (as in FIG. 2), spacers 104 are formed alongsidewalls of control gate layer 42. For example, as seen in FIG. 9,control gate layer 42 includes two sidewalls between select gates 24 and30, in which a first sidewall is closer to select gate 24 rather thanselect gate 30 and a second sidewall is closer to select gate 30 ratherthan select gate 24. In one embodiment, spacers 104 are formed on thesesidewalls by forming an insulating layer and then performing ananisotropic etch. They may be formed using a dielectric material, suchas an oxide or a nitride. After formation of spacers 104, an implant 106is performed, which is similar to implant 44. Implant 106 is performedwith an energy (or strength) such that a fraction of the dopants willpenetrate through control gate layer 42 into substrate 12 to result indoped regions 108 and 109 but not penetrate ARC layers 26 and 32 andcontrol gate layer 42 in regions 13 and 17. Therefore, doped region 108in region 15 is similar to doped region 46 (and can have similar dopanttypes and concentrations) but is laterally shifted inwards at both endsdue to the presence of spacers 104. Spacers 104 add thickness abovecontrol gate layer 42 that prevents the dopants from penetrating intosubstrate 12 under the spacers. Therefore, doped region 108 is spacedapart from select gates 24 and 30 farther than doped region 46 is spacedapart from select gates 24 and 30. The thickness of spacers 104 can becontrolled to change the width of region 15 and thus control the widthof doped region 108.

FIG. 10 illustrates a cross-sectional view of semiconductor 100 at asubsequent processing stage. After implant 106, spacers 104 are removed.Therefore, note that spacers 104 may be referred to as sacrificialspacers. After removal of spacers 104, ARC layer 50 is formed overcontrol gate layer 42. ARC layer 50 includes an insulating layer, suchas nitride or oxynitride

FIG. 11 illustrates a cross-sectional view of semiconductor 100 at asubsequent processing stage. After removal of spacers 104, thesubsequent processing may be the same as described above in reference toFIGS. 4-6 to form split gate devices 64 and 66. As with doped regions 46and 94, doped region 108 extends under the corner formed by control gate54 at the second sidewall of control gate 54, adjacent S/D region 80,and under the corner formed by control gate 60 at the second sidewall ofcontrol gate 60, adjacent S/D region 80. Therefore, doped region 108similarly shields the trapped charges, thus reducing their effects onthe devices.

FIG. 12 illustrates a cross-sectional view of semiconductor structure100 according to alternate embodiment. Referring back to the processingstage of FIG. 1, in which control gate layer 42 has been formedconformally over charge storage layer 40, rather than performing implant44 (as in FIG. 2), ARC layer 50 is first formed over control gate layer42. After forming ARC layer 50, spacers 110 are formed along sidewallsof ARC layer 50, similar to spacers 104 formed on sidewalls of controlgate layer 42. For example, as seen in FIG. 12, ARC layer 50 includestwo sidewalls between select gates 24 and 30, in which a first sidewallis closer to select gate 24 rather than select gate 30 and a secondsidewall is closer to select gate 30 rather than select gate 24. In oneembodiment, spacers 110 are formed on these sidewalls of ARC layer 50 byforming an insulating layer and then performing an anisotropic etch.They may be formed using a dielectric material, such as an oxide or anitride. After formation of spacers 110, an implant 111 is performed,which is similar to implant 44. Implant 111 is performed with an energy(or strength) such that a fraction of the dopants will penetrate throughcontrol gate layer 42 into substrate 12 to result in doped regions 112and 113 but not penetrate ARC layers 26 and 32 and control gate layer 42in regions 13 and 17. Therefore, doped region 112 in region 15 issimilar to doped region 108 (and can have similar dopant types andconcentrations) but is laterally shifted inwards at both ends due to thepresence of ARC layer 50 under spacers 110. The added thickness of ARClayer 50 before the implant makes regions 13 and 17 wider and region 15narrower.

FIG. 13 illustrates a cross-sectional view of semiconductor 100 at asubsequent processing stage processed in accordance to the alternateembodiment described in FIG. 12. That is, the subsequent processing maybe the same as described above in reference to FIGS. 4-6 to form splitgate devices 64 and 66. Note that during this subsequent processing, aswith spacers 104, spacers 110 are removed and may also be referred to assacrificial spacers. Therefore, depending on the desired width of dopedregion 108 and 112, the implant 106 or 111 may be performed before orafter formation of ARC layer 50 over control gate layer 42. As withdoped region 106, doped region 112 extends under the corner formed bycontrol gate 54 at the second sidewall of control gate 54 and adjacentS/D region 80 and under the corner formed by control gate 60 at thesecond sidewall of control gate 60 and adjacent S/D region 80.Therefore, doped region 112 similarly shields the trapped charges, thusreducing their effects on the devices.

FIG. 14 illustrates a cross-sectional view of a semiconductor device 110according to an alternate embodiment in which like numerals indicatelike elements. Referring back to the processing stage of FIG. 3, priorto pattering ARC layer 50, control gate layer 42, and charge storagelayer 40, a second implant 114 is performed after the first implant 44.That is, implant 44 is performed, as described above, and ARC layer 50is then formed over charge storage layer 42. After formation of ARClayer 50, implant 114 is performed resulting in doped region 116 whichis narrower than doped region 46. As with implant 44, implant 114 isperformed with an energy (or strength) such that a fraction of thedopants will penetrate ARC layers 26 and 32 and through control gatelayer 42 into substrate 12 to result in doped regions 116 and 117 butnot penetrate ARC layers 26 and 32 and control gate layer 42 in regions13 and 17. Therefore, doped region 116 in region 15 overlaps region 46but is narrower. This allows stepped or more graded dopant profiles tobe formed at the end of regions 46 and 116 when so desired.

FIG. 15 illustrates a cross-sectional view of semiconductor 110 at asubsequent processing stage. After implant 114, the subsequentprocessing may be the same as described above in reference to FIGS. 4-6to form split gate devices 64 and 66. As with doped region 46, dopedregions 46 and 116 extend under the corner formed by control gate 54 atthe second sidewall of control gate 54, adjacent S/D region 80, andunder the corner formed by control gate 60 at the second sidewall ofcontrol gate 60, adjacent S/D region 80. Therefore, doped regions 46 and116 similarly shields the trapped charges, thus reducing their effectson the devices.

In the embodiments described above, after performing the implant toresult in doped regions 46, 94, 108, 112, and 116, an anneal may beperformed in which heat diffusion laterally moves the edges of the dopedregions closer to control gates 54 and 60 (i.e. widens the dopedregions). In this case, the doped regions can be closer to the controlgates for better shielding of the trapped charges without having toimplant so close to the control gate edge. The use of the ARC layer andsacrificial spacers also help ensure that the implant is not too closeto the control gate edges near the select gates because if too close,the implants can damage the layers.

Therefore, by now it can be appreciated how the effects of trap-up canbe reduced through a selective implant through part of the control gatelayer to place dopants at the channel surface region near the sourceedge. The placement of the dopants can be controlled by, for example,controlling the strength of the implant, the timing of the implant (e.g.before or after ARC layer formation), and through the use of sacrificialspacers. In this manner, the trapped charges can be shielded to reducetheir undesirable effects on the device.

Although the invention has been described with respect to specificconductivity types or polarity of potentials, skilled artisansappreciated that conductivity types and polarities of potentials may bereversed.

Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under”and the like in the description and in the claims, if any, are used fordescriptive purposes and not necessarily for describing permanentrelative positions. It is understood that the terms so used areinterchangeable under appropriate circumstances such that theembodiments of the invention described herein are, for example, capableof operation in other orientations than those illustrated or otherwisedescribed herein.

Although the invention is described herein with reference to specificembodiments, various modifications and changes can be made withoutdeparting from the scope of the present invention as set forth in theclaims below. For example, the structure of the nonvolatile memoryincluding split gate devices 64 and 66 can have a variety of differentcircuit designs. Accordingly, the specification and figures are to beregarded in an illustrative rather than a restrictive sense, and allsuch modifications are intended to be included within the scope of thepresent invention. Any benefits, advantages, or solutions to problemsthat are described herein with regard to specific embodiments are notintended to be construed as a critical, required, or essential featureor element of any or all the claims.

The term “coupled,” as used herein, is not intended to be limited to adirect coupling or a mechanical coupling.

Furthermore, the terms “a” or “an,” as used herein, are defined as oneor more than one. Also, the use of introductory phrases such as “atleast one” and “one or more” in the claims should not be construed toimply that the introduction of another claim element by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim element to inventions containing only one such element,even when the same claim includes the introductory phrases “one or more”or “at least one” and indefinite articles such as “a” or “an.” The sameholds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used toarbitrarily distinguish between the elements such terms describe. Thus,these terms are not necessarily intended to indicate temporal or otherprioritization of such elements.

The following are various embodiments of the present invention.

In one embodiment, a method of forming a semiconductor device using asubstrate, includes forming a first isolation region in the substrate, afirst select gate over the substrate, a second select gate over thesubstrate spaced from the first select gate, a charge storage layer overthe substrate including over the first and second select gates, and acontrol gate layer over the charge storage layer whereby the controlgate layer has a top surface further from a top surface of the substrate(1) in a first region over and laterally adjacent to the first selectgate and (2) in a second region over and laterally adjacent to thesecond select gate than in a third region between the first and secondselect gates; performing a first implant with a strength sufficient toreach the substrate in the third region to form a doped region in thesubstrate and not sufficient to reach the substrate in the first andsecond regions; and removing the control gate layer over a first portionof the doped region between the first select gate and the second selectgate to leave a first control gate over the substrate adjacent to thefirst select gate and over a second portion of the doped region to leavea second control gate over the substrate adjacent to the second selectgate and over a third portion of the doped region. In one aspect, themethod includes forming an insulating layer over the control gate layer;wherein the performing the first implant is performed after forming theinsulating layer. In a further aspect, the method further includesremoving the insulating layer over the first portion of the doped regionprior to the removing of the control gate layer over the first portionof the doped region. In yet a further aspect, the insulating layer has afirst sidewall between the first and second select gates and a secondsidewall between the first and second select gates, the first sidewallis closer to the first select gate than the second select gate, and thesecond sidewall is closer to the second select gate than the firstselect gate, and the method further includes forming a first sidewallspacer on the first sidewall and a second sidewall spacer on the secondsidewall, wherein the first and second sidewall spacers are formed priorto the performing the first implant. In another yet further aspect, thecontrol gate layer has a first sidewall between the first and secondselect gates and a second sidewall between the first and second selectgates, the first sidewall of the control gate layer is closer to thefirst select gate than the second select gate, and the second sidewallof the select gate layer is closer to the second select gate than thefirst select gate, and the method further includes forming a thirdsidewall spacer on the first sidewall of the control gate layer and afourth sidewall spacer on the second sidewall of the control gate layer,wherein the third and fourth sidewall spacers are formed prior to theperforming the implant. In a further aspect, the method further includesperforming a second implant prior to forming the insulating layer. Inanother further aspect, the second implant is performed after formingthe second and third sidewall spacers. In another aspect of the aboveembodiment, the method further includes forming a first anti-reflectivecoating over the first select gate and second anti-reflective coatingover the second select gate prior to forming the charge storage layer.

In another embodiment, a method of forming a semiconductor device usinga substrate, includes forming a first select gate over the substrate;forming a second select gate, spaced from the first select gate, overthe substrate; forming a charge storage layer over the first selectgate, over the second select gate, and over the substrate in a regionbetween the first select gate and the second select gate, wherein thecharge storage layer is conformal; forming a control gate layer over thecharge storage layer, wherein the control gate layer is conformal;performing a first implant that penetrates through the control gatelayer in a middle portion of the region between the first select gateand the second select gate to the substrate to form a doped region inthe substrate in a first portion of the region between the first selectgate and the second select gate that does not reach the first selectgate and does not reach the second select gate. In one aspect, themethod further includes forming a first insulating layer over thecontrol gate layer. In a further aspect, the performing the firstimplant occurs after forming the first insulating layer. In yet afurther aspect, the performing the first implant occurs before formingthe first insulating layer. In yet even a further aspect, the methodfurther includes performing a second implant after forming the firstinsulating layer. In another aspect of the another embodiment, thecontrol gate layer has a first sidewall and a second sidewall betweenthe first select gate and the second select gate, and the method furtherincludes forming a first sidewall spacer on the first sidewall; forminga second sidewall spacer on the second sidewall; wherein the performingthe first implant occurs after the forming the first sidewall spacer andthe forming the second sidewall spacer. In a further aspect, the methodfurther includes forming a first insulating layer over the control gatelayer, wherein the first insulating layer is conformal; and performing asecond implant through the first insulating later and into a secondportion of the region between the first select gate and the secondselect gate that is within the first portion and less than the firstportion. In another aspect, the insulating layer has a first sidewalland a second sidewall between the first select gate and the secondselect gate, and the method further includes forming a first sidewallspacer on the first sidewall; and forming a second sidewall spacer onthe second sidewall; wherein the performing the first implant occursafter the forming the first sidewall spacer and the forming the secondsidewall spacer. In another further aspect, the charge storage layerincludes nanocrystals.

18. In yet another embodiment, a non-volatile memory structure includesa first select gate over a substrate; a second select gate over thesubstrate; a first charge storage layer along a first sidewall of afirst side of the first select gate and over a first portion of thesubstrate adjacent to the first select gate; a second charge storagelayer along a first sidewall of a first side of the second select gateand over a second portion of the substrate adjacent to the second selectgate; a first source/drain region in the substrate on a second side ofthe first select gate; a second source/drain region in the substrate ona second side of the second select gate; a first control gate over thefirst charge storage layer where the first charge storage layer is overthe first portion of the substrate, wherein the first control gate has afirst side along the first charge storage layer, and the first controlgate has a second side; a second control gate over the second chargestorage layer where the second charge storage layer is over the secondportion of the substrate, wherein the second control gate has a firstside along the second charge storage layer, and the second control gatehas a second side; a third source/drain region in the substrate betweenthe second side of the first control gate and the second side of thesecond control gate; a first doped region in the substrate extendingfrom the third source/drain region to under the first control gate to apoint at least a fourth of the way across the first control gate; and asecond doped region in the substrate extending from the thirdsource/drain region to under the second control gate to a point at leasta fourth of the way across the second control gate, wherein the first,second, and third source/drain regions have a first depth and a firstconductivity type, and the first and second doped regions have a seconddepth, which is less than one fourth of the first depth, and the firstconductivity type. In one aspect, the structure further includes a wellformed in the substrate and having a second conductivity type, whereinthe first, second, and third source/drains and the first and seconddoped regions are in the well. In a further aspect, the structurefurther includes a third doped region in the third source/drain regionconnecting the first and second doped regions, wherein the third dopedregion has the second depth.

What is claimed is:
 1. A method of forming a semiconductor device usinga substrate, comprising: forming a first isolation region in thesubstrate, a first select gate over the substrate, a second select gateover the substrate spaced from the first select gate, a charge storagelayer over the substrate including over the first and second selectgates, and a control gate layer over the charge storage layer wherebythe control gate layer has a top surface further from a top surface ofthe substrate (1) in a first region over and laterally adjacent to thefirst select gate and (2) in a second region over and laterally adjacentto the second select gate than in a third region between the first andsecond select gates; performing a first implant with a strengthsufficient to reach the substrate in the third region to form a dopedregion in the substrate and not sufficient to reach the substrate in thefirst and second regions; and removing the control gate layer over afirst portion of the doped region between the first select gate and thesecond select gate to leave a first control gate over the substrateadjacent to the first select gate and over a second portion of the dopedregion to leave a second control gate over the substrate adjacent to thesecond select gate and over a third portion of the doped region.
 2. Themethod of claim 1 comprising: forming an insulating layer over thecontrol gate layer; wherein: the performing the first implant isperformed after forming the insulating layer.
 3. The method of claim 2,further comprising removing the insulating layer over the first portionof the doped region prior to the removing of the control gate layer overthe first portion of the doped region.
 4. The method of claim 3, whereinthe insulating layer has a first sidewall between the first and secondselect gates and a second sidewall between the first and second selectgates, the first sidewall is closer to the first select gate than thesecond select gate, and the second sidewall is closer to the secondselect gate than the first select gate, further comprising: forming afirst sidewall spacer on the first sidewall and a second sidewall spaceron the second sidewall, wherein the first and second sidewall spacersare formed prior to the performing the first implant.
 5. The method ofclaim 4, wherein the control gate layer has a first sidewall between thefirst and second select gates and a second sidewall between the firstand second select gates, the first sidewall of the control gate layer iscloser to the first select gate than the second select gate, and thesecond sidewall of the select gate layer is closer to the second selectgate than the first select gate, further comprising: forming a thirdsidewall spacer on the first sidewall of the control gate layer and afourth sidewall spacer on the second sidewall of the control gate layer,wherein the third and fourth sidewall spacers are formed prior to theperforming the implant.
 6. The method of claim 5 further comprisingperforming a second implant prior to forming the insulating layer. 7.The method of claim 6, wherein the second implant is performed afterforming the second and third sidewall spacers.
 8. The method of claim 1,further comprising forming a first anti-reflective coating over thefirst select gate and second anti-reflective coating over the secondselect gate prior to forming the charge storage layer.
 9. A method offorming a semiconductor device using a substrate, comprising: forming afirst select gate over the substrate; forming a second select gate,spaced from the first select gate, over the substrate; forming a chargestorage layer over the first select gate, over the second select gate,and over the substrate in a region between the first select gate and thesecond select gate, wherein the charge storage layer is conformal;forming a control gate layer over the charge storage layer, wherein thecontrol gate layer is conformal; performing a first implant thatpenetrates through the control gate layer in a middle portion of theregion between the first select gate and the second select gate to thesubstrate to form a doped region in the substrate in a first portion ofthe region between the first select gate and the second select gate thatdoes not reach the first select gate and does not reach the secondselect gate.
 10. The method of claim 9 further comprising forming afirst insulating layer over the control gate layer.
 11. The method ofclaim 10, wherein the performing the first implant occurs after formingthe first insulating layer.
 12. The method of claim 10, wherein theperforming the first implant occurs before forming the first insulatinglayer.
 13. The method of claim 12, further comprising performing asecond implant after forming the first insulating layer.
 14. The methodof claim 9, wherein the control gate layer has a first sidewall and asecond sidewall between the first select gate and the second selectgate, further comprising: forming a first sidewall spacer on the firstsidewall; forming a second sidewall spacer on the second sidewall;wherein the performing the first implant occurs after the forming thefirst sidewall spacer and the forming the second sidewall spacer. 15.The method of claim 14 further comprising: forming a first insulatinglayer over the control gate layer, wherein the first insulating layer isconformal; and performing a second implant through the first insulatinglater and into a second portion of the region between the first selectgate and the second select gate that is within the first portion andless than the first portion.
 16. The method of claim 10 wherein theinsulating layer has a first sidewall and a second sidewall between thefirst select gate and the second select gate, further comprising:forming a first sidewall spacer on the first sidewall; and forming asecond sidewall spacer on the second sidewall; wherein the performingthe first implant occurs after the forming the first sidewall spacer andthe forming the second sidewall spacer.
 17. The method of claim 9,wherein the charge storage layer comprises nanocrystals.
 18. Anon-volatile memory structure, comprising: a first select gate over asubstrate; a second select gate over the substrate; a first chargestorage layer along a first sidewall of a first side of the first selectgate and over a first portion of the substrate adjacent to the firstselect gate; a second charge storage layer along a first sidewall of afirst side of the second select gate and over a second portion of thesubstrate adjacent to the second select gate; a first source/drainregion in the substrate on a second side of the first select gate; asecond source/drain region in the substrate on a second side of thesecond select gate; a first control gate over the first charge storagelayer where the first charge storage layer is over the first portion ofthe substrate, wherein the first control gate has a first side along thefirst charge storage layer, and the first control gate has a secondside; a second control gate over the second charge storage layer wherethe second charge storage layer is over the second portion of thesubstrate, wherein the second control gate has a first side along thesecond charge storage layer, and the second control gate has a secondside; a third source/drain region in the substrate between the secondside of the first control gate and the second side of the second controlgate; a first doped region in the substrate extending from the thirdsource/drain region to under the first control gate to a point at leasta fourth of the way across the first control gate; and a second dopedregion in the substrate extending from the third source/drain region tounder the second control gate to a point at least a fourth of the wayacross the second control gate, wherein the first, second, and thirdsource/drain regions have a first depth and a first conductivity type,and the first and second doped regions have a second depth, which isless than one fourth of the first depth, and the first conductivitytype.
 19. The non-volatile memory structure of claim 18, furthercomprising a well formed in the substrate and having a secondconductivity type, wherein the first, second, and third source/drainsand the first and second doped regions are in the well.
 20. Thenon-volatile memory structure of claim 19 further comprising a thirddoped region in the third source/drain region connecting the first andsecond doped regions, wherein the third doped region has the seconddepth.